Special Section on Secure Computer Architectures

COMPUTER architectures are profoundly affected by a new security landscape, caused by the dramatic evolution of information technology over the past decade. First, secure computer architectures have to support a wide range of security applications that extend well beyond the desktop environment, and that also include handheld, mobile, and embedded architectures, as well as high-end computing servers. Second, secure computer architectures have to support new applications of information security and privacy, as well as new information security standards. Third, secure computer architectures have to be protected and be tamperresistant at multiple abstraction levels, covering network, software, and hardware. This Special Section in Transactions on Computers aims to capture this evolving landscape of secure computing architectures, to build a vision of opportunities and unresolved challenges. Following an open call for papers, we received 30 submissions from authors in 18 different countries and on a broad range of topics related to secure computer architectures. After a preliminary screening, each submission was assigned to three reviewers. After the first round of reviews, we selected the six top-ranked papers for further consideration in the Special Section. These six papers were revised as a ‘minor revision’ by the authors. All six papers were eventually accepted into the Special Section. Among the remaining submissions, 11 papers were revised as a ‘major revision’ in the second round of reviews. These papers may eventually appear in a regular issue of IEEE Transactions on Computers, but they did notmeet the timeline or threshold for this Special Section. The first paper, “Hybrid Obfuscation to Protect against Disclosure Attacks on Embedded Microprocessors,” by M. Fyrbiak et al., presents a technique to protect embedded software against code reverse-engineering. The paper also proposes statistical metrics to determine the quality of the protection. The second paper, “On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography,” by J. Howe et al., proposes a comprehensive hardware evaluation of discrete Gaussian Samplers, a key building block for the next generation of lattice-based cryptography. The third paper, “Hardware/Software co-Design of an Accelerator for FV Homomorphic Encryption Scheme using Karatsuba Algorithm,” by V. Migliore et al., proposes a hardware-accelerated implementation the Somewhat Homomorphic Encryption (SHE) scheme, using fast polynomial arithmetic with the FFT algorithm. The fourth paper, “Bitstream Fault Injections (BiFI) Automated Fault Attacks against SRAM-based FPGAs,” by P. Swierczynski et al., demonstrates how the malicious modification of a bitstream can be used to mount an efficient fault attack on a cryptographic primitive integrated into an unknown FPGA bitstream. The fifth paper, “Hardware-Based Trusted Computing Architectures for Isolation and Attestation,” by P. Maene et al., makes a comprehensive analysis of recently proposed computer architectures and emphasizes on features used to enable isolation and attestation. The final paper, “GliFreD: Glitch-Free DuplicationTowards Power-Equalized Circuits on FPGAs,” by A. Moradi et al., proposes a dual-rail precharge implementation, suitable for mapping into a Field Programmable Gate Array, which supports the implementation of a hiding-based sidechannel countermeasure. Overall, the six papers of this Special Section capture the state of the art in physical and logical security of computer architectures. We are grateful to the submitting authors of all 30 submissions to this Special Section.We also sincerely thank the numerous anonymous reviewers who assisted with the selection of the papers for the Special Section. Finally, we are very grateful to the Editor in Chief and the staff of IEEE Transactions on Computers who enabled this Special Section and assisted uswith the practical implementation.